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PCF8563
Real-time clock/calendar
Rev. 06 -- 21 February 2008 Product data sheet
1. General description
The PCF8563 is a CMOS real-time clock/calendar optimized for low power consumption. A programmable clock output, interrupt output and voltage-low detector are also provided. All addresses and data are transferred serially via a two-line bidirectional I2C-bus. Maximum bus speed is 400 kbit/s. The built-in word address register is incremented automatically after each written or read data byte.
2. Features
I Provides year, month, day, weekday, hours, minutes and seconds based on 32.768 kHz quartz crystal I Century flag I Clock operating voltage: 1.8 V to 5.5 V I Low backup current; typical 0.25 A at VDD = 3.0 V and Tamb = 25 C I 400 kHz two-wire I2C-bus interface (at VDD = 1.8 V to 5.5 V) I Programmable clock output for peripheral devices (32.768 kHz, 1024 Hz, 32 Hz and 1 Hz) I Alarm and timer functions I Integrated oscillator capacitor I Internal power-on reset I I2C-bus slave address: read A3h and write A2h I Open-drain interrupt pin I ElectroStatic Discharge (ESD) protection exceeds 2000 V Human Body Model (HBM) per JESD22-A114, 200 V Machine Model (MM) per JESD22-A115 and 2000 V Charged Device Model (CDM) per JESD22-C101 I Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA
3. Applications
I I I I Mobile telephones Portable instruments Electronic metering Battery powered products
NXP Semiconductors
PCF8563
Real-time clock/calendar
4. Ordering information
Table 1. Ordering information Package Name DIP8 SO8 TSSOP8 HVSON10 Description plastic dual in-line package; 8 leads (300 mil) plastic small outline package; 8 leads; body width 3.9 mm plastic thin shrink small outline package; 8 leads; body width 3 mm plastic thermal enhanced very thin small outline package; no leads; 10 terminals; body 3 x 3 x 0.85 mm Version SOT97-1 SOT96-1 SOT505-1 SOT650-1 Type number Topside mark PCF8563P PCF8563T PCF8563TS PCF8563BS PCF8563P 8563T 8563 8563S
5. Block diagram
OSCI OSCILLATOR 32.768 kHz OSCO MONITOR 00 01 0D POWER ON RESET TIME 02 03 VDD VSS 04 05 06 07 WATCH DOG 08 VL_SECONDS MINUTES HOURS DAYS WEEKDAYS CENTURY_MONTHS YEARS CONTROL CONTROL_STATUS_1 CONTROL_STATUS_2 CLKOUT_CONTROL DIVIDER CLOCK OUT CLKOUT
ALARM FUNCTION 09 0A SDA SCL I2C-BUS INTERFACE 0B 0C MINUTE_ALARM HOUR_ALARM DAY_ALARM WEEKDAY_ALARM INTERRUPT TIMER FUNCTION INT
PCF8563
0E 0F
TIMER_CONTROL TIMER
001aah658
Fig 1.
Block diagram
PCF8563_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 21 February 2008
2 of 32
NXP Semiconductors
PCF8563
Real-time clock/calendar
6. Pinning information
6.1 Pinning
OSCI OSCO INT VSS
1 2
8 7
VDD CLKOUT SCL SDA
OSCI OSCO INT VSS
1 2
8 7
VDD CLKOUT SCL SDA
PCF8563P
3 4
001aaf977
PCF8563T
6 5 3 4
001aaf975
6 5
Fig 2.
Pin configuration DIP8
Fig 3.
Pin configuration SO8
terminal 1 index area OSCI OSCO n.c. OSCI OSCO INT VSS 1 2 3 4
001aaf976
1 2 3 4 5
10 n.c. 9 VDD CLKOUT SCL SDA
PCF8563BS
8 7 6
8 7
VDD CLKOUT SCL SDA
INT VSS
PCF8563TS
6 5
001aaf981
Transparent top view
Fig 4.
Pin configuration TSSOP8
Fig 5.
Pin configuration HVSON10
OSCI
1
8
VDD
OSCO
2
7
CLKOUT
INT
3
6
SCL
VSS
4
5
SDA
PCF8563
mgr886
Fig 6.
Device diode protection diagram
PCF8563_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 21 February 2008
3 of 32
NXP Semiconductors
PCF8563
Real-time clock/calendar
6.2 Pin description
Table 2. Symbol OSCI OSCO n.c. INT VSS SDA SCL CLKOUT VDD n.c. Pin description Pin DIP8, SO8, TSSOP8 1 2 3 4 5 6 7 8 HVSON10 1 2 3 4 5 6 7 8 9 10 oscillator input oscillator output not connected interrupt output (open-drain; active LOW) ground serial data input and output serial clock input clock output, open-drain positive supply voltage not connected Description
7. Functional description
The PCF8563 contains sixteen 8-bit registers with an auto-incrementing address register, an on-chip 32.768 kHz oscillator with one integrated capacitor, a frequency divider which provides the source clock for the Real-Time Clock/calender (RTC), a programmable clock output, a timer, an alarm, a voltage-low detector and a 400 kHz I2C-bus interface. All 16 registers are designed as addressable 8-bit parallel registers although not all bits are implemented. The first two registers (memory address 00h and 01h) are used as control and/or status registers. The memory addresses 02h through 08h are used as counters for the clock function (seconds up to years counters). Address locations 09h through 0Ch contain alarm registers which define the conditions for an alarm. Address 0Dh controls the CLKOUT output frequency. 0Eh and 0Fh are the timer control and timer registers, respectively. The seconds, minutes, hours, days, weekdays, months, years as well as the minute alarm, hour alarm, day alarm and weekday alarm registers are all coded in Binary Coded Decimal (BCD) format. When one of the RTC registers is read the contents of all counters are frozen. Therefore, faulty reading of the clock/calendar during a carry condition is prevented.
7.1 Alarm function modes
By clearing the MSB of one or more of the alarm registers (bit AE = Alarm Enable), the corresponding alarm condition(s) will be active. In this way an alarm can be generated from once per minute up to once per week. The alarm condition sets the Alarm Flag (AF). The asserted AF can be used to generate an interrupt (on pin INT). The AF can only be cleared by software.
PCF8563_6
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Product data sheet
Rev. 06 -- 21 February 2008
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NXP Semiconductors
PCF8563
Real-time clock/calendar
7.2 Timer
The 8-bit countdown timer at address 0Fh is controlled by the timer control register at address 0Eh. The timer control register determines one of 4 source clock frequencies for the timer (4096 Hz, 64 Hz, 1 Hz, or 160 Hz), and enables or disables the timer. The timer counts down from a software-loaded 8-bit binary value. At the end of every countdown, the timer sets the Timer Flag (TF). The TF may only be cleared by software. The asserted TF can be used to generate an interrupt (on pin INT). The interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal which follows the state of TF. Bit TI_TP is used to control this mode selection. When reading the timer, the current countdown value is returned.
7.3 Clock output
A programmable square wave is available at pin CLKOUT. Operation is controlled by the CLKOUT control register at address 0Dh. Frequencies of 32.768 kHz (default), 1024 Hz, 32 Hz and 1 Hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator. CLKOUT is an open-drain output and enabled at power-on. If disabled it becomes high-impedance.
7.4 Reset
The PCF8563 includes an internal reset circuit which is active whenever the oscillator is stopped. In the reset state the I2C-bus logic is initialized and all registers are reset according to Table 25.
7.5 Voltage-low detector
The PCF8563 has an on-chip voltage-low detector (see Figure 7). When VDD drops below Vlow, bit VL in the seconds register is set to indicate that the integrity of the clock information is no longer guaranteed. The VL flag can only be cleared by software. Bit VL is intended to detect the situation when VDD is decreasing slowly, for example under battery operation. Should VDD reach Vlow before power is re-asserted then bit VL is set. This will indicate that the time may be corrupted.
mgr887
VDD normal power operation period of battery operation
Vlow t
VL set
Fig 7.
Voltage-low detection
PCF8563_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 21 February 2008
5 of 32
NXP Semiconductors
PCF8563
Real-time clock/calendar
7.6 Register organization
Table 3. Formatted registers overview Bit positions labelled as x are not relevant. Bit positions labelled with 0 should always be written with logic 0; if read they could be either logic 0 or logic 1. Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh Register name control_status_1 control_status_2 VL_seconds minutes hours days weekdays century_months years minute_alarm hour_alarm day_alarm weekday_alarm CLKOUT_control timer_control timer AE AE AE AE FE TE x x x x x x x x Bit 7 TEST1 0 VL x x x x C x x x x x x x Bit 6 0 0 Bit 5 STOP 0 Bit 4 0 TI_TP Bit 3 TESTC AF Bit 2 0 TF Bit 1 0 AIE Bit 0 0 TIE
x x x x x x x x x FD1 TD1 FD0 TD0

7.6.1 Control_status_1 register
Table 4. Bit 7 6 5 Control_status_1 - Control and Status register 1 (address 00h) bit description Symbol TEST1 0 STOP 0 1 4 3 0 TESTC 0 1 2 to 0 0 Value 0 1 Description Normal mode EXT_CLK test mode default value is logic 0 RTC source clock runs all RTC divider chain flip-flops are asynchronously set to logic 0; the RTC clock is stopped (CLKOUT at 32.768 kHz is still available) default value is logic 0 Power-on reset override facility is disabled; set to logic 0 for normal operation Power-on reset override may be enabled default value is logic 0
7.6.2 Control_status_2 register
Bits TF and AF: When an alarm occurs, AF is set to logic 1. Similarly, at the end of a timer countdown, TF is set to logic 1. These bits maintain their value until overwritten by software. If both timer and alarm interrupts are required in the application, the source of the interrupt can be determined by reading these bits. To prevent one flag being overwritten while clearing another a logic AND is performed during a write access.
PCF8563_6
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Product data sheet
Rev. 06 -- 21 February 2008
6 of 32
NXP Semiconductors
PCF8563
Real-time clock/calendar
Bits TIE and AIE: These bits activate or deactivate the generation of an interrupt when TF or AF is asserted, respectively. The interrupt is the logical OR of these two conditions when both AIE and TIE are set.
Table 5. Bit 7 to 5 4 Control_status_2 - Control and Status register 2 (address 01h) bit description Symbol 0 TI_TP 0 1 Value Description default value is logic 0 INT is active when TF is active (subject to the status of TIE) INT pulses active according to Table 6 (subject to the status of TIE); note that if AF and AIE are active then INT will be permanently active alarm flag inactive alarm flag active alarm flag is cleared alarm flag remains unchanged timer flag inactive timer flag active timer flag is cleared timer flag remains unchanged alarm interrupt disabled alarm interrupt enabled timer interrupt disabled timer interrupt enabled
3
AF
0 (read) 1 (read) 0 (write) 1 (write)
2
TF
0 (read) 1 (read) 0 (write) 1 (write)
1 0
AIE TIE
0 1 0 1
Table 6.
INT operation (bit TI_TP = 1) INT period (s)[1] n = 1[2] n > 1[2]
1 1 1 1 4096 64 64 64 1 8192 1 128 1 64 1 64
Source clock (Hz) 4096 64 1
1 60
[1] [2]
TF and INT become active simultaneously. n = loaded countdown value. Timer stopped when n = 0.
7.6.3 Time and date registers
Table 7. Bit 7 6 to 0 VL_seconds - Validity and Seconds register (address 02h) bit description Symbol VL SECONDS[6:0] Value 0 1 00 to 59 Description clock integrity is guaranteed integrity of the clock information is no longer guaranteed the current seconds, coded in BCD format. Example: seconds register contains x101 1001 = 59 seconds
PCF8563_6
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Product data sheet
Rev. 06 -- 21 February 2008
7 of 32
NXP Semiconductors
PCF8563
Real-time clock/calendar
Minutes - Minutes register (address 03h) bit description Symbol x MINUTES[6:0] 00 to 59 Value Description not relevant the current minutes, coded in BCD format
Table 8. Bit 7 6 to 0 Table 9. Bit 7 to 6 5 to 0 Table 10. Bit 7 to 6 5 to 0
[1]
Hours - Hours register (address 04h) bit description Symbol x HOURS[5:0] 00 to 23 Value Description not relevant the current hours, coded in BCD format
Days - Days register (address 05h) bit description Symbol x DAYS[5:0] 01 to 31 Value Description not relevant the current day, coded in BCD format[1]
The PCF8563 compensates for leap years by adding a 29th day to February if the year counter contains a value which is exactly divisible by 4, including the year 00.
Table 11. Bit 7 to 3 2 to 0[1]
[1]
Weekdays - Weekdays register (address 06h) bit description Symbol x WEEKDAYS[2:0] 0 to 6 Value Description not relevant the current weekday, coded in BCD format, see Table 12.
These bits may be re-assigned by the user.
Table 12. Weekday Sunday Monday Tuesday
Weekday assignments Bit 7 x x x x x x x Bit 6 x x x x x x x Bit 5 x x x x x x x Bit 4 x x x x x x x Bit 3 x x x x x x x Bit 2 0 0 0 0 1 1 1 Bit 1 0 0 1 1 0 0 1 Bit 0 0 1 0 1 0 1 0
Wednesday Thursday Friday Saturday Table 13. Bit 7
Century_months - Century and Months register (address 07h) bit description Symbol C[1] 0 1 Value Description century; this bit is toggled when the years register overflows from 99 to 00 indicates the century is 20xx indicates the century is 19xx not relevant 01 to 12 the current month, coded in BCD format, see Table 14
6 to 5 4 to 0
[1]
x MONTHS[4:0]
This bit may be re-assigned by the user.
PCF8563_6
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Product data sheet
Rev. 06 -- 21 February 2008
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NXP Semiconductors
PCF8563
Real-time clock/calendar
Month assignments Bit 7 C C C C C C C C C C C C Bit 6 x x x x x x x x x x x x Bit 5 x x x x x x x x x x x x Bit 4 0 0 0 0 0 0 0 0 0 1 1 1 Bit 3 0 0 0 0 0 0 0 1 1 0 0 0 Bit 2 0 0 0 1 1 1 1 0 0 0 0 0 Bit 1 0 1 1 0 0 1 1 0 0 0 0 1 Bit 0 1 0 1 0 1 0 1 0 1 0 1 0
Table 14. Month January February March April May June July August September October November December Table 15. Bit 7 to 0
Years - Years register (address 08h) bit description Symbol YEARS[7:0] Value 00 to 99 Description the current year, coded in BCD format
7.6.4 Alarm registers
When one or more of these registers are loaded with a valid minute, hour, day or weekday and its corresponding bit Alarm Enable (AE) is logic 0, then that information will be compared with the current minute, hour, day and weekday. When all enabled comparisons first match, the Alarm Flag (AF) is set. AF will remain set until cleared by software. Once AF has been cleared it will only be set again when the time increments to match the alarm condition once more. Alarm registers which have their bit AE at logic 1 will be ignored.
Table 16. Bit 7 6 to 0 Minute_alarm - Minute alarm register (address 09h) bit description Symbol AE Value 0 1 ALARM _MINUTES[6:0] 00 to 59 Description minute alarm is enabled minute alarm is disabled the minute alarm information, coded in BCD format
Table 17. Bit 7 6 5 to 0
Hour_alarm - Hour alarm register (address 0Ah) bit description Symbol AE x ALARM_HOURS[5:0] 00 to 23 Value 0 1 Description hour alarm is enabled hour alarm is disabled not relevant the hour alarm information, coded in BCD format
PCF8563_6
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Product data sheet
Rev. 06 -- 21 February 2008
9 of 32
NXP Semiconductors
PCF8563
Real-time clock/calendar
Day_alarm - Day alarm register (address 0Bh) bit description Symbol AE x ALARM_DAYS[5:0] 01 to 31 Value 0 1 Description day alarm is enabled day alarm is disabled not relevant the day alarm information, coded in BCD format
Table 18. Bit 7 6 5 to 0 Table 19. Bit 7 6 to 3 2 to 0
Weekday_alarm - Weekday alarm register (address 0Ch) bit description Symbol AE x ALARM_ WEEKDAYS[2:0] 0 to 6 Value 0 1 Description weekday alarm is enabled weekday alarm is disabled not relevant the weekday alarm information, coded in BCD format
7.6.5 Clock output control register
Table 20. Bit 7 CLKOUT_control - CLKOUT control register (address 0Dh) bit description Symbol FE Value 0 1 6 to 2 1 to 0 x FD[1:0] see Table 21 Description the CLKOUT output is inhibited and set to high-impedance the CLKOUT output is activated not relevant these bits control the frequency output at pin CLKOUT
Table 21. FD1 0 0 1 1
FD1 and FD0: CLKOUT frequency selection FD0 0 1 0 1 CLKOUT frequency 32.768 kHz 1024 Hz 32 Hz 1 Hz
7.6.6 Countdown timer
The timer register is an 8-bit binary countdown timer. It is enabled and disabled via the timer control register bit TE. The source clock for the timer is also selected by the timer control register. Other timer properties such as interrupt generation are controlled via control_status_2 register. For accurate read back of the countdown value, the I2C-bus clock (SCL) must be operating at a frequency of at least twice the selected timer clock.
PCF8563_6
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Product data sheet
Rev. 06 -- 21 February 2008
10 of 32
NXP Semiconductors
PCF8563
Real-time clock/calendar
Timer_control - Timer control register (address 0Eh) bit description Symbol TE x TD[1:0] see Table 23 Value 0 1 Description timer is disabled timer is enabled not relevant timer source clock frequency select; these bits determine the source clock for the countdown timer; when not in use, TD[1:0] should be set to 11 (160 Hz) for power saving
Table 22. Bit 7 6 to 2 1 to 0
Table 23. TD1 0 0 1 1 Table 24. Bit 7 to 0
TD1 and TD0: Timer frequency selection TD0 0 1 0 1 TIMER Source clock frequency 4096 Hz 64 Hz 1 Hz
1 60
Hz
Timer - Timer value register (address 0Fh) bit description Symbol TIMER Value 00h to FFh Description countdown value = n; n CountdownPeriod = -------------------------------------------------------------SourceClockFrequency
7.7 EXT_CLK test mode
A Test mode is available which allows for on-board testing. In such a mode it is possible to set up test conditions and control the operation of the RTC. The Test mode is entered by setting bit TEST1 in control_status_1 register. Then pin CLKOUT becomes an input. The Test mode replaces the internal 64 Hz signal with the signal applied to pin CLKOUT. Every 64 positive edges applied to pin CLKOUT will then generate an increment of one second. The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a minimum period of 1000 ns. The internal 64 Hz clock, now sourced from CLKOUT, is divided down to 1 Hz by a 26 divide chain called a pre-scaler. The pre-scaler can be set into a known state by using bit STOP. When bit STOP is set, the pre-scaler is reset to 0 (STOP must be cleared before the pre-scaler can operate again). From a STOP condition, the first 1 second increment will take place after 32 positive edges on CLKOUT. Thereafter, every 64 positive edges will cause a one-second increment. Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock. When entering the Test mode, no assumption as to the state of the pre-scaler can be made.
PCF8563_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 21 February 2008
11 of 32
NXP Semiconductors
PCF8563
Real-time clock/calendar
Operation example: 1. Set EXT_CLK test mode (control_status_1, bit TEST1 = 1) 2. Set STOP (control_status_1, bit STOP = 1) 3. Clear STOP (control_status_1, bit STOP = 0) 4. Set time registers to desired value 5. Apply 32 clock pulses to CLKOUT 6. Read time registers to see the first change 7. Apply 64 clock pulses to CLKOUT 8. Read time registers to see the second change Repeat steps 7 and 8 for additional increments.
7.8 Power-On Reset (POR) override
The POR duration is directly related to the crystal oscillator start-up time. Due to the long start-up times experienced by these types of circuits, a mechanism has been built in to disable the POR and hence speed up on-board test of the device. The setting of this mode requires that the I2C-bus pins, SDA and SCL, be toggled in a specific order as shown in Figure 8. All timings are required minimums. Once the Override mode has been entered, the device immediately stops being reset and normal operation may commence i.e. entry into the EXT_CLK test mode via I2C-bus access. The Override mode may be cleared by writing a logic 0 to TESTC. TESTC must be set to logic 1 before re-entry into the Override mode is possible. Setting TESTC to logic 0 during normal operation has no effect except to prevent entry into the POR override mode.
500 ns SDA
2000 ns
SCL 8 ms power up override active
mgm664
Fig 8.
POR override sequence
Table 25 shows the register reset values.
Table 25. Address 00h 01h 02h 03h 04h Register reset value[1] Register name control_status_1 control_status_2 VL_seconds minutes hours Bit 7 0 x 1 1 x Bit 6 0 x x x x Bit 5 0 0 x x x Bit 4 0 0 x x x Bit 3 1 0 x x x Bit 2 0 0 x x x Bit 1 0 0 x x x Bit 0 0 0 x x x
PCF8563_6
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Product data sheet
Rev. 06 -- 21 February 2008
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NXP Semiconductors
PCF8563
Real-time clock/calendar
Register reset value[1] ...continued Register name days weekdays century_months years minute_alarm hour_alarm day_alarm weekday_alarm CLKOUT_control timer_control timer Bit 7 x x x x 1 1 1 1 1 0 x Bit 6 x x x x x x x x x x x Bit 5 x x x x x x x x x x x Bit 4 x x x x x x x x x x x Bit 3 x x x x x x x x x x x Bit 2 x x x x x x x x x x x Bit 1 x x x x x x x x 0 1 x Bit 0 x x x x x x x x 0 1 x
Table 25. Address 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh
[1]
registers marked `x' are undefined at power-up and unchanged by subsequent resets.
8. Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Figure 9).
SDA
SCL data line stable; data valid change of data allowed
mbc621
Fig 9.
Bit transfer
8.2 Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P); see Figure 10.
PCF8563_6
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Product data sheet
Rev. 06 -- 21 February 2008
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NXP Semiconductors
PCF8563
Real-time clock/calendar
SDA
SDA
SCL S START condition P STOP condition
SCL
mbc622
Fig 10. Definition of start and stop conditions
8.3 System configuration
A device generating a message is a transmitter, a device receiving a message is a receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves (see Figure 11).
SDA SCL MASTER TRANSMITTER / RECEIVER SLAVE TRANSMITTER / RECEIVER MASTER TRANSMITTER / RECEIVER
mba605
SLAVE RECEIVER
MASTER TRANSMITTER
Fig 11. System configuration
8.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH-level signal put on the bus by the transmitter during which time the master generates an extra acknowledge-related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter (see Figure 12). The device that acknowledges must pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.
PCF8563_6
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Product data sheet
Rev. 06 -- 21 February 2008
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NXP Semiconductors
PCF8563
Real-time clock/calendar
data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition clock pulse for acknowledgement
mbc602
1
2
8
9
Fig 12. Acknowledgement on the I2C-bus
8.5 I2C-bus protocol
8.5.1 Addressing
Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. The PCF8563 acts as a slave receiver or slave transmitter. Therefore the clock signal SCL is only an input signal, but the data signal SDA is a bidirectional line. The PCF8563 slave address is shown in Figure 13.
1
0
1
0
0
0
1
R/W
group 1
group 2
mce189
Fig 13. Slave address
8.5.2 Clock/calendar read/write cycles
The I2C-bus configuration for the different PCF8563 read and write cycles is shown in Figure 14, Figure 15 and Figure 16. The word address is a 4-bit value that defines which register is to be accessed next. The upper four bits of the word address are not used.
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Product data sheet
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NXP Semiconductors
PCF8563
Real-time clock/calendar
acknowledgement from slave
acknowledgement from slave
acknowledgement from slave
S
SLAVE ADDRESS
0A
WORD ADDRESS
A
DATA
A
P
R/W
n bytes auto increment memory word address
mbd822
Fig 14. Master transmits to slave receiver (Write mode)
acknowledgement from slave
acknowledgement from slave
acknowledgement from slave
acknowledgement from master
S
SLAVE ADDRESS
0A
WORD ADDRESS
A
S
SLAVE ADDRESS
1A
DATA
A
R/W
at this moment master transmitter becomes master receiver and PCA8563 slave receiver becomes slave transmitter
R/W
n bytes auto increment memory word address
no acknowledgement from master
DATA
1
P
last byte auto increment memory word address
001aag133
Fig 15. Master reads after setting word address (write word address; read data)
acknowledgement from slave
acknowledgement from master
no acknowledgement from master
S
SLAVE ADDRESS
1A
DATA
A
DATA
1
P
R/W
n bytes auto increment word address
last byte auto increment word address
mgl665
Fig 16. Master reads slave immediately after first byte (Read mode)
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Product data sheet
Rev. 06 -- 21 February 2008
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PCF8563
Real-time clock/calendar
9. Limiting values
Table 26. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD IDD VI VO II IO Ptot Tamb Tstg Parameter supply voltage supply current input voltage output voltage input current output current total power dissipation ambient temperature storage temperature on pins SCL and SDA on pin OSCI on pins CLKOUT and INT at any input at any output Conditions Min -0.5 -50 -0.5 -0.5 -0.5 -10 -10 -40 -65 Max +6.5 +50 +6.5 VDD + 0.5 +6.5 +10 +10 300 +85 +150 Unit V mA V V V mA mA mW C C
10. Static characteristics
Table 27. Static characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +85 C; fosc = 32.768 kHz; quartz Rs = 40 k; CL = 8 pF; unless otherwise specified. Symbol Supplies VDD supply voltage interface inactive; fSCL = 0 Hz; Tamb = 25 C; see Figure 20 interface active; fSCL = 400 kHz; see Figure 20 clock data integrity; Tamb = 25 C IDD supply current interface active; see Figure 19 fSCL = 400 kHz fSCL = 100 kHz interface inactive (fSCL = 0 Hz); CLKOUT disabled; Tamb = 25 C; see Figure 17 VDD = 5.0 V VDD = 3.0 V VDD = 2.0 V interface inactive (fSCL = 0 Hz); CLKOUT disabled; Tamb = -40 C to +85 C; see Figure 17 VDD = 5.0 V VDD = 3.0 V VDD = 2.0 V
[2] [2] [1]
Parameter
Conditions
Min 1.0 1.8 Vlow -
Typ -
Max 5.5 5.5 5.5 800 200
Unit V V V A A
[1]
-
275 250 225
550 500 450
nA nA nA
-
500 400 400
750 650 600
nA nA nA
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Table 27. Static characteristics ...continued VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +85 C; fosc = 32.768 kHz; quartz Rs = 40 k; CL = 8 pF; unless otherwise specified. Symbol IDD Parameter supply current Conditions interface inactive (fSCL = 0 Hz); CLKOUT enabled at 32 kHz; Tamb = 25 C; see Figure 18 VDD = 5.0 V VDD = 3.0 V VDD = 2.0 V interface inactive (fSCL = 0 Hz); CLKOUT enabled at 32 kHz; Tamb = -40 C to +85 C; see Figure 18 VDD = 5.0 V VDD = 3.0 V VDD = 2.0 V Inputs VIL VIH ILI Ci Outputs IOL LOW-level output current VOL = 0.4 V; VDD = 5 V on pin SDA on pin INT on pin CLKOUT IOH ILO HIGH-level output current output leakage current low voltage on pin CLKOUT; VOH = 4.6 V; VDD = 5 V VO = VDD or VSS -3 -1 -1 1 -1 0 +1 mA mA mA mA A LOW-level input voltage HIGH-level input voltage input leakage current input capacitance VI = VDD or VSS
[3] [2] [2]
Min
Typ
Max
Unit
-
825 550 425
1600 1000 800
nA nA nA
VSS 0.7VDD -1 -
950 650 500 0 -
1700 1100 900 0.3VDD VDD +1 7
nA nA nA V V A pF
Voltage detector Vlow
[1] [2] [3]
Tamb = 25 C; sets bit VL; see Figure 7
-
0.9
1.0
V
For reliable oscillator start-up at power-up: VDD(min)power-up = VDD(min) + 0.3 V. Timer source clock = 160 Hz, level of pins SCL and SDA is VDD or VSS. Tested on sample basis.
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1 IDD (A) 0.8
mgr888
1 IDD (A) 0.8
mgr889
0.6
0.6
0.4
0.4
0.2
0.2
0 0 2 4 VDD (V) 6
0 0 2 4 VDD (V) 6
Tamb = 25 C; Timer = 1 minute.
Tamb = 25 C; Timer = 1 minute.
Fig 17. Supply current IDD as a function of supply voltage VDD; CLKOUT disabled
mgr890
Fig 18. Supply current IDD as a function of supply voltage VDD; CLKOUT = 32 kHz
mgr891
1 IDD (A) 0.8
4 frequency deviation (ppm) 2
0.6 0 0.4 -2 0.2 -4 0 -40 0 40 80 120
T (C)
0
2
4
VDD (V)
6
VDD = 3 V; Timer = 1 minute.
Tamb = 25 C; normalized to VDD = 3 V.
Fig 19. Supply current IDD as a function of temperature T; CLKOUT = 32 kHz
Fig 20. Frequency deviation as a function of supply voltage VDD
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11. Dynamic characteristics
Table 28. Dynamic characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +85 C; fosc = 32.768 kHz; quartz Rs = 40 k; CL = 8 pF; unless otherwise specified. Symbol Oscillator CL(itg) fosc/fosc integrated load capacitance relative oscillator frequency variation VDD = 200 mV; Tamb = 25 C 15 25 2x 10-7 35 pF Parameter Conditions Min Typ Max Unit
Quartz crystal parameters (f = 32.768 kHz) Rs CL Ctrim CLKOUT I2C-bus fSCL tHD;STA tSU;STA tLOW tHIGH tr tf Cb tSU;DAT tHD;DAT tSU;STO tw(spike)
[1] [2] [3] [4]
series resistance load capacitance trimmer capacitance duty cycle on pin CLKOUT timing characteristics (see Figure 21) SCL clock frequency hold time (repeated) START condition set-up time for a repeated START condition LOW period of the SCL clock HIGH period of the SCL clock rise time of both SDA and SCL signals fall time of both SDA and SCL signals capacitive load for each bus line data set-up time data hold time set-up time for STOP condition spike pulse width on bus SDA SCL SDA SCL
[1] [2][3] [4]
parallel 5 0.6 0.6 1.3 0.6 100 0 0.6 -
10 50 -
40 25 400 0.3 0.3 0.3 0.3 400 50
k pF pF % kHz s s s s s s s s pF ns ns s ns
CLKOUT output
Unspecified for fCLKOUT = 32.768 kHz. All timing values are valid within the operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage swing of VSS to VDD. A detailed description of the I2C-bus specification, with applications, is given in brochure The I2C-bus specification. This brochure may be ordered using the code 9398 393 40011. I2C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second.
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SDA
t BUF
t LOW
tf
SCL
t HD;STA
tr
t HD;DAT
t HIGH
t SU;DAT
SDA
t SU;STA t SU;STO
mga728
Fig 21. I2C-bus timing waveforms
12. Application information
VDD
SDA MASTER TRANSMITTER/ RECEIVER
1F
SCL
VDD SCL CLOCK CALENDAR OSCI OSCO
PCF8563
SDA VSS VDD
R
R
R: pull-up resistor tr R= Cb
SDA SCL (I2C-bus)
mgm665
Fig 22. Application diagram
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12.1 Quartz frequency adjustment
12.1.1 Method 1: fixed OSCI capacitor
By evaluating the average capacitance necessary for the application layout, a fixed capacitor can be used. The frequency is best measured via the 32.768 kHz signal available after power-on at pin CLKOUT. The frequency tolerance depends on the quartz crystal tolerance, the capacitor tolerance and the device-to-device tolerance (on average 5 x 10-6). Average deviations of 5 minutes per year can be easily achieved.
12.1.2 Method 2: OSCI trimmer
Using the 32.768 kHz signal available after power-on at pin CLKOUT, fast setting of a trimmer is possible.
12.1.3 Method 3: OSCO output
Direct measurement of OSCO out (accounting for test probe capacitance).
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13. Package outline
DIP8: plastic dual in-line package; 8 leads (300 mil) SOT97-1
D seating plane
ME
A2
A
L
A1
c Z e b1 wM (e 1) b2 5 MH
b 8
pin 1 index E
1
4
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.14 0.068 0.045 b1 0.53 0.38 0.021 0.015 b2 1.07 0.89 0.042 0.035 c 0.36 0.23 0.014 0.009 D (1) 9.8 9.2 0.39 0.36 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 1.15 0.045
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT97-1 REFERENCES IEC 050G01 JEDEC MO-001 JEITA SC-504-8 EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-13
Fig 23. Package outline SOT97-1 (DIP8)
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SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A X
c y HE vMA
Z 8 5
Q A2 A1 pin 1 index Lp 1 e bp 4 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
0.010 0.057 0.004 0.049
0.019 0.0100 0.014 0.0075
0.244 0.039 0.028 0.041 0.228 0.016 0.024
8o o 0
ISSUE DATE 99-12-27 03-02-18
Fig 24. Package outline SOT96-1 (SO8)
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TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
SOT505-1
D
E
A
X
c y HE vMA
Z
8
5
A2 pin 1 index
A1
(A3)
A
Lp L
1
e bp
4
detail X wM
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.45 0.25 c 0.28 0.15 D(1) 3.1 2.9 E(2) 3.1 2.9 e 0.65 HE 5.1 4.7 L 0.94 Lp 0.7 0.4 v 0.1 w 0.1 y 0.1 Z(1) 0.70 0.35 6 0
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT505-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-04-09 03-02-18
Fig 25. Package outline SOT505-1 (TSSOP8)
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HVSON10: plastic thermal enhanced very thin small outline package; no leads; 10 terminals; body 3 x 3 x 0.85 mm
SOT650-1
0
1 scale
2 mm
X D B A
A E A1 c detail X
terminal 1 index area
terminal 1 index area 1 L
e1 e b 5 vMCAB wMC y1 C
C y
Eh
10 Dh DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D(1) 3.1 2.9 Dh 2.55 2.15 E(1) 3.1 2.9
6
Eh 1.75 1.45
e 0.5
e1 2
L 0.55 0.30
v 0.1
w 0.05
y 0.05
y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT650-1 REFERENCES IEC --JEDEC MO-229 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-01-22 02-02-08
Fig 26. Package outline SOT650-1 (HVSON10)
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14. Handling information
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling MOS devices; see JESD625-A and/or IEC61340-5.
15. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
15.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
15.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
15.3 Wave soldering
Key characteristics in wave soldering are:
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* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities 15.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 27) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 29 and 30
Table 29. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 30. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 27.
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temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 27. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
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16. Revision history
Table 31. Revision history Release date 20080221 Data sheet status Product data sheet Change notice Supersedes PCF8563_5 Document ID PCF8563_6 Modifications: PCF8563_5 Modifications:
* * * * * * * *
Register names modified in Figure 1 and various tables. Figure 17, Figure 18 and Figure 19: corrected the unit on the vertical axis. Product data sheet PCF8563-04 The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Quick reference data table removed to comply with guidelines. Table 3: Table 3 and Table 4 combined in one table. Section 4: added topside mark. Section 4: added HVSON10 package. Product data Product data Product data Objective specification PCF8563-03 PCF8563-02 PCF8563_N_1 -
20070717
PCF8563-04 (9397 750 12999) PCF8563-03 (9397 750 11158) PCF8563-02 (9397 750 04855) PCF8563_N_1 (9397 750 03282)
20040312 20030414 19990416 19980325
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17. Legal information
17.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
17.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
18. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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Real-time clock/calendar
19. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.6.6 7.7 7.8 8 8.1 8.2 8.3 8.4 8.5 8.5.1 8.5.2 9 10 11 12 12.1 12.1.1 12.1.2 12.1.3 13 14 15 15.1 15.2 15.3 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Alarm function modes. . . . . . . . . . . . . . . . . . . . 4 Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Voltage-low detector . . . . . . . . . . . . . . . . . . . . . 5 Register organization . . . . . . . . . . . . . . . . . . . . 6 Control_status_1 register . . . . . . . . . . . . . . . . . 6 Control_status_2 register . . . . . . . . . . . . . . . . . 6 Time and date registers . . . . . . . . . . . . . . . . . . 7 Alarm registers . . . . . . . . . . . . . . . . . . . . . . . . . 9 Clock output control register . . . . . . . . . . . . . . 10 Countdown timer. . . . . . . . . . . . . . . . . . . . . . . 10 EXT_CLK test mode . . . . . . . . . . . . . . . . . . . . 11 Power-On Reset (POR) override . . . . . . . . . . 12 Characteristics of the I2C-bus. . . . . . . . . . . . . 13 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Start and stop conditions . . . . . . . . . . . . . . . . 13 System configuration . . . . . . . . . . . . . . . . . . . 14 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 14 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 15 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Clock/calendar read/write cycles . . . . . . . . . . 15 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17 Static characteristics. . . . . . . . . . . . . . . . . . . . 17 Dynamic characteristics . . . . . . . . . . . . . . . . . 20 Application information. . . . . . . . . . . . . . . . . . 21 Quartz frequency adjustment . . . . . . . . . . . . . 22 Method 1: fixed OSCI capacitor . . . . . . . . . . . 22 Method 2: OSCI trimmer. . . . . . . . . . . . . . . . . 22 Method 3: OSCO output . . . . . . . . . . . . . . . . . 22 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23 Handling information. . . . . . . . . . . . . . . . . . . . 27 Soldering of SMD packages . . . . . . . . . . . . . . 27 Introduction to soldering . . . . . . . . . . . . . . . . . 27 Wave and reflow soldering . . . . . . . . . . . . . . . 27 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 27 15.4 16 17 17.1 17.2 17.3 17.4 18 19 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 30 31 31 31 31 31 31 32
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 21 February 2008 Document identifier: PCF8563_6

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